1. Field of the Invention
This invention relates generally to computers. More particularly, the present invention relates to a branch prediction architecture.
2. Description of the Related Art
To maximize performance, modern computer designs attempt to execute as many instructions as possible concurrently. To find enough instructions to keep busy, the processors in modern computers use branch prediction to guess which instructions will be executed.
Branch prediction accuracy is a major performance factor in modern computer processor design. To improve branch prediction, various branch prediction strategies have been studied and implemented. See, for example, McFarling, "Serial Branch Prediction" (Nov. 1996); Su and Zhou, "A Comparative Analysis of Branch Prediction Schemes", Computer Science Division, University of California at Berkeley (undated); Evers, Chang, and Patt, "Using Hybrid Branch Predictors to Improve Branch Prediction Accuracy in the Presence of Context Switches", Department of Electrical Engineering and Computer Science, The University of Michigan (undated); Patel, Friendly, and Patt, "Critical Issues Regarding the Trace Cache Fetch Mechanism", Advanced Computer Architecture Laboratory, Department of Electrical Engineering and Computer Science, The University of Michigan (undated); and Yeh, Marr, and Patt, "Increasing the Instruction Fetch Rate via Multiple Branch Prediction and a Branch Address Cache", The 7th ACM International Conference on Supercomputing, Tokyo, Japan (July 1993). The sophisticated branch predictor implementations described in these papers use various different strategies, in various combinations, to achieve greater branch prediction accuracy.
The branch predictor is but one part, albeit an important part, of an overall branch prediction architecture. It is the overall branch prediction architecture's job to accurately and quickly guess which instructions will be executed, a job that becomes more and more complicated with each increase in computer speed, depth of pipeline, and number of instruction bundles. Although the known architectures are satisfactory for state-of-the-art microprocessors, they are not optimum for future processors that will be designed to process many more instructions concurrently, at much higher speeds.
The present invention is directed to overcoming, or at least reducing, these problems, and to provide a branch prediction architecture for future generation microprocessors.